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| 78p2344jat 4-port e3/ds3/sts-1 liu with jitter attenuator preliminary datasheet - 1 - july 2003 description the 78p2344jat is a low-power, 4-port ds3/e3/sts1 line interface unit (liu) with integrated jitter attenuator (jat). it includes clock recovery and transmitter pulse shaping functions for applications using 75-ohm coaxial cable at distances up to 1350 feet. these applications include dslams, t1,3/e1,3 digital multiplexers, sonet add/drop multiplexers, pdh equipment, ds3 to fiber optic and microwave modems and atm wan access for routers and switches. the receiver recovers clock and data from a b3zs or hdb3 coded ami signal. it can compensate for over 12db of cable and 6db of flat loss. the transmitter generates a signal that meets the standard pulse shape requirements. it has a b3zs/hdb3 endec with a receive line code violation detector, a loop-back mode, an input receive mux that can select a redundant channel, a clock polarity selection mode, and the ability to receive a dsx3 monitor signal. standards ? jitter tolerance: telcordia gr-499-core [ds3] and gr-253-core [sts1], itu-t g.823 [e3] and g.824 [ds3] ? loss of signal: itu-t g.775 ? jitter transfer: etsi tbr-24 1997 [e3]; telcordia gr-499-core [ds3] and gr-253- core [ds3/sts1] features ? transmit and receive interfaces for e3, ds3 and sts-1 applications ? designed for use with 75 ohm coaxial cable up to 1350 ft long end-to-end or up to 900 ft long from a ds3 cross-connect ? receives ds3-high and dsx3 monitor signals ? local and remote loopback ? selectable b3zs/hdb3 endec with line code violation detector ? standards-based los function ? optional serial-port based mode selection and channel status monitoring ? receiver agc corrects for up to 6db of flat loss ? adaptive digital clock recovery (uses line-rate reference clock input) ? receive output clock maintains nominal line-rate frequency at all times ? fully integrated jitter attenuation function provided for all line rates (no external vcxo required) ? jitter attenuator configurable for transmit or receive path ? transmit line fault monitor ? requires no external current-setting resistor or loop filter components ? single 3.3v supply operation ? available in 100-pin exposed pad jedec lqfp block diagram linn linp loutn loutp tpos tneg tclk rclk rpos rneg ds3 txen llbka llbkb rlbk pdtx endec signals from adjacent port txnw control registers cs sck sdi sdo e3 lbo master bias generator ckref each channel ckref los mon attenuator power distribution b3zs / hdb3 encoder data detector b3zs / hdb3 decoder adaptive equalizer signal detector transmit monitor pulse shaper controls jitter attenuator flags tclkp rclkp clock recovery agc pdrx
78p2344jat 4-port e3/ds3/sts-1 liu with jitter attenuator - 2 - functional description the 78p2344jat contains all the necessary transmit and receive circuitry for connection between e3, ds3, or sts-1 line interfaces and digital framer/mapper ics. operating rate the master control register (mscr) determines which mode the device operates in according to the table below. the msl0 pin is also provided for mode selection in applications without a serial control interface. upon power-up or reset, the state of the msl0 pin is sensed and mapped into the ds3 and e3 register bits representing the appropriate mode of operation. after power-up/reset, the state of the msl0 pin is ignored. standard msl0 pin ds3 bit e3 bit e3 l 0 1 ds3 h 1 0 sts-1 z 0 0 sts-1 z 1 1 receiver operation the receiver input is either transformer-coupled or capacitor-coupled to the line signal. in applications where the highest performance and isolation are required, a 1:1 transformer is used in the receive path. in applications where isolation is provided elsewhere in the circuit, capacitor coupling can be used. the receiver input should be line terminated externally with a termination resistor. the ami signal first enters an agc, which has a selectable gain range setting. in normal operation, the agc can compensate for signals with up to 6db of flat loss. when receiver monitor mode is enabled, the agc can compensate for a dsx3 monitor signal with 16 to 20 db of flat loss. the signal then enters a high performance adaptive equalizer. the equalizer is designed to overcome inter-symbol interference caused by long cable lengths. because the equalizer is adaptive, the circuit will work with all square-shaped signals such as ds3-high or 34.368 mbit/s e3. the variable gain differential amplifier automatically controls the gain to maintain a constant voltage level output regardless of the input voltage level. the outputs of the data comparators are connected to the clock recovery circuits. the clock recovery system employs a digital pll, which uses a line-rate reference clock frequency applied to the ckref pin. the jitter tolerance of 78p2344 meets the requirements of itu-t g.823 for e3 rates; the requirements of itu-t g.824, gr-499 (cat i and ii) for ds3 rates; and the requirements of gr-253 for sts1 rates. without the jitter attenuator, the jitter transfer function meets the requirements of gr-499 for category ii ds3 interfaces. when the jitter attenuator is enabled, the 78p2344jat meets the requirements of gr-499 and gr-253 for all categories of ds3/sts1 equipment and the etsi tbr-24 requirements for e3 rates. to check conformance with other standards, please refer to the jitter attenuator transfer function section for more detailed info. receiver monitor mode when in monitor mode, 20db of flat gain is applied to the incoming signal before it is fed to the receive equalizer. this mode is controlled by the mon bit in the mode control register. 78p2344jat 4-port e3/ds3/sts-1 liu with jitter attenuator - 3 - local loopback and redundancy mux each receiver has a 4-input mux as shown in the adjacent figure. in multiport applications where redundant channels are required, the receiver mux can be configured to provide the necessary multiplexing functions. this allows the user to use one port as a redundant monitor for the other port. the tables below show the register settings for selecting the desired receiver input source. llbka (port 1) llbkb (port 1) receiver #1 input source 0 0 linp1/linn1 0 1 loutp1/loutn1 1 0 linp2/linn2 1 1 loutp2/loutn2 llbka (port 2) llbkb (port 2) receiver #2 input source 0 0 linp2/linn2 0 1 loutp2/loutn2 1 0 linp1/linn1 1 1 loutp1/loutn1 llbka (port 3) llbkb (port 3) receiver #3 input source 0 0 linp3/linn3 0 1 loutp3/loutn3 1 0 linp4/linn4 1 1 loutp4/loutn4 llbka (port 4) llbkb (port 4) receiver #4 input source 0 0 linp4/linn4 0 1 loutp4/loutn4 1 0 linp3/linn3 1 1 loutp3/loutn3 note : the llbka and llbkb bits are located in the mode control register (mdcr). the register control bit, regen, should be enabled when using the register settings to avoid conflict with external loopback setting pins. transmitter #1 receiver #1 00 01 10 11 transmitter #2 receiver #2 00 01 10 11 transmitter #3 receiver #3 00 01 10 11 transmitter #4 receiver #4 00 01 10 11 loutp1, loutn1 linp1, linn1 loutp2, loutn2 linp2, linn2 loutp3, loutn3 linp3, linn3 loutp4, loutn4 linp4, linn4 llbka,b(1) llbka,b(2) llbka,b(3) llbka,b(4) when serial interface control is not available, the respective lpbkx pin for each of the channels can also be used to activate local loopback mode as shown below. note that redundant channel modes can only be activated using the serial interface. lpbkx pin loopback mode l normal operation same as llbka,b = ?00? z remote (digital) loopback same as rlbk = ?1? h local (analog) loopback same as llbka,b = ?01? 78p2344jat 4-port e3/ds3/sts-1 liu with jitter attenuator - 4 - signal detect when the received signal is below a minimum threshold, the corresponding los signal (bit) is asserted. a time delay is provided before this output is active so that transient interruptions do not cause false indications. the los signal can also be used to trigger an interrupt on the intrx pin when serial interface control is not available. this is controlled by setting the rxer bit in the interrupt control register (intc). note: in ds3 or sts-1 mode, when lbo is not enabled, the transmitters have to be properly terminated to ensure reliable los detection. if a transmitter is not terminated, the resultant 2x signal is large enough to couple to the neighboring receivers through the esd diodes, causing false signal detect indication. b3zs/hdb3 endec with line code violation detect the 78p2344jat includes a selectable b3zs/hdb3 encoder/decoder (endec). the endec function can be enabled or disabled through pin selection or register setting. when the endec is enabled, the decoder generates a composite nrz logic data stream following the b3zs (for ds3/sts-1) or hdb3 (for e3) substitution codes via the rpos pin as shown below: endec endec endec endec bit/pin rposx rnegx 0 / l nrz data receive line code violation indicator 1 / h positive ami negative ami the decoder also detects receive line code violations (rlcv) and outputs a pulse via the rneg pin. three different classes of line code violations are detected. 1) too many zeros: more than two (three) consecutive zeros in b3zs (hdb3) mode. 2) not enough zeros between bipolar pulse (b) and bipolar violation pulse (v): (b,v) for b3zs. (b,v) or (b,0,v) for hdb3. 3) code violation: even number of bipolar pulses (b) detected between bipolar violation pulses (v). on the transmit side, when the endec is enabled, nrz input data is encoded to positive and negative ami logic data following the b3zs (for ds3/sts-1) or hdb3 (for e3) substitution codes. the nrz data is input to the tpos pin as shown below: endec endec endec endec bit/pin tposx tnegx 0 / l nrz data ?don?t care? 1 / h positive ami negative ami transmitter operation transmitters 1-4 are enabled by their corresponding txen bit. when enabled, each transmitter accepts logic level clock (tclkx), positive data (tposx) and negative data (tnegx) signals and generates current pulses on the loutpx and loutnx pins. when properly connected to a 1:2ct center-tapped transformer, an ami pulse is generated which can drive a 75 ? coaxial cable. when the recommended transformer is used and when ds3 mode is selected, the transmitted pulse shape at the end of the 75 ? terminated cable of 0 to 450 feet will fit the ds3 template in ansi t1.102- 1993 and telcordia gr-499-core standard documents. for sts-1 applications, the transmitted pulse for a short cable meets the requirements of telcordia gr-253-core. for e3 applications, the transmitted pulse for a short cable meets the requirements of itu-t g.703. in either ds3 and sts-1 modes, the lbox pin or lbo bit should be set high for short cable (< 225 ft), and should be set low for long cable (> 225 ft). the lbo settings are ignored in e3 mode. rclk/tclk polarity reversal to simplify the interface with various framer circuitry, tclk polarity can be internally inverted by setting the tclkp bit, and rclk polarity can be inverted by setting the rclkp bit. both bits are located in the master control register (mscr). remote (digital) loopback when the register control bit, regen, is disabled and the lpbkx pin is floating; or when the register control bit, regen, is enabled and the rlbk bit is set, rclkx, rnegx, and rposx outputs are internally looped back to the tclkx, tnegx, and tposx inputs respectively. 78p2344jat 4-port e3/ds3/sts-1 liu with jitter attenuator - 5 - line build-out the line build-out (lbo) function controls the transmit amplitude and pulse shape in ds3 and sts-1 modes. the selection of lbo depends on the amount of cable the transmitter is connected to. when less than 225 ft of cable is used, the corresponding lbox pin or lbo bit should be high. when 225ft or more cable is used the corresponding lbo setting (lbox pin or lbo bit) should be low. lbo can be controlled either from pins or from register settings, depending on the status of the register control bit, regen. transmit enable the txen bit in the mode control register controls the transmitter output. when logic zero, the transmitter output is disabled. this feature is used to disable ports as well as to multiplex two or more transceivers to one port. the transmitter of any port can also be disabled by floating the respective lbox pin, in which case it will also power-down the entire transmitter. see section on the power-down function for more info. transmit monitor the transmit monitor function detects activity on the transmitter output at the loutpx and loutnx pins. when there is a transmitter fault, in the case of an open or short on the chip, the transformer, or the circuit board, the transmit signal amplitude will be altered. the transmit monitor detects the amplitude of the driven signal. the txnw signal (bit) goes high when the amplitude of the transmit signal is outside a valid amplitude range. when the signal amplitude is either too high or too low for longer than a specified duration, the txnw bit goes high. the txnw signal can be also used to trigger an interrupt on the intrx pin when serial interface control is not available. this is accomplished by setting the txer bit in the interrupt control register (intc). jitter attenuator jitter attenuation function is provided on-chip. the jitter attenuator can be configured to be in the transmit or the receive path. when configured in the transmit path, the input clock at tclk pin is passed through a very low bandwidth digital pll. the corresponding transmit data is buffered into a fifo and clocked out using the de-jittered output clock of the pll. when configured in the receive path, the recovered clock is passed through the low bandwidth digital pll, and the corresponding receive data is buffered into the fifo and clocked out using the de-jittered clock. the jitter attenuator can be configured independently for each channel by writing to the jitter attenuator control register (jacr) as follows: jaen bit jasl bit jitter attenuator mode 0 x jitter attenuator disabled 1 0 jitter attenuator configured to be in the receive path 1 1 jitter attenuator configured to be in the transmit path when serial interface control is not available, the msl1 pin is provided for jitter attenuator mode selection. upon power-up or reset, the state of the msl1 pin is sensed and mapped into the jaen and jasl register bits for all channels, representing the appropriate mode of operation. after power-up or reset, the state of the msl1 pin is ignored. the state of the msl1 pin, and the corresponding jitter attenuator configuration is shown below. msl1 pin jitter attenuator mode l jitter attenuator in receive path h jitter attenuator in transmit path z jitter attenuator disabled pll bandwidth a pll response with effectively one pole below 27 hz is adequate to meet the etsi tbr24 e3 standards. a pll response with one pole below 40 hz is adequate to meet the gr-499 (cat i) ds3 standards. either of the two bandwidths can be selected via register setting. in either high or low bandwidth mode, the pll bandwidth is proportional to the data rate as follows: line rate jabw bit pll bandwidth (hz) 0 13 e3 1 188 0 17 ds3 1 245 0 20 sts1 1 283 the default state of the jabw bit depends on which line-rate is selected through the msl0 pin. if e3 or ds3 mode is selected, the default state is ?0?. if sts1 mode is selected, the default state is ?1?. 78p2344jat 4-port e3/ds3/sts-1 liu with jitter attenuator - 6 - elastic store depth to optimize the trade-off between data latency and clock wander tolerance, the fifo elastic store depth can be selected through the serial port by writing to the jitter attenuator control register (jacr) as follows: esp[1:0] bits elastic store depth 00 pass-through mode 01 16 ui 10 32 ui 11 64 ui (default) the elastic store depth selects the nominal fifo read pointer address. the total or maximum elastic store depth is set to be twice as deep as the nominal pointer address. the circular buffer length is always twice as long as the nominal pointer address. power-down function power-down control is provided to allow the transceivers to be shut off individually. transmit and receive power-down can be set independently via the pdtx and pdrx bits in the mode control register. floating the respective lbox pin can also set pdtx for each channel. the serial control interface and configuration registers are not affected by power-down. internal power-on reset the 78p2344jat includes on-chip power-on reset (por) function to ensure the serial-port registers are initialized to known default states upon power-up. this reset signal also sets all state machines within the transceivers to nominal operational states. the internal reset signal is also brought out to the por pin. this pin is a multi-function pin which allows for the following: 1) override the internal por signal by driving in an external active-low reset signal; 2) monitor the state of the internal por signal (for test and debug only); 3) add external capacitor to delay the release of the internal power-on reset signal to allow the msl0 pin to stabilize prior to release of reset (approximately 8 s per nf added). the internal resistance of the por pin is approximately 5k ? . serial control interface the serial port controlled register allows a generic controller to interface with the 78p2344jat. it is used for mode settings, diagnostics and test, and the retrieval of status and performance information. the serial interface consists of four pins: chip select (cs), serial clock (sck), serial data in (sdi), and serial data out (sdo). the cs pin initiates the read and write operations. it can also be used to select a particular device allowing sck, sdi and sdo to be bussed together. sck is the clock input that times the data on sdi and sdo. data on sdi is latched in on the rising-edge of sck, and data on sdo is clocked out using the falling edge of sck. sdi is used to insert mode, address, and register data into the chip. address and data information are input least significant bit (lsb) first. sdo is a tristate capable output. it is used to output register data during a read operation. sdo output is normally high impedance, and is enabled only during the duration when register data is being clocked out. read data is clocked out least significant bit (lsb) first. if sdi coming out of the micro-controller chip is also tristate capable, sdi and sdo can be connected together to simplify connections. the maximum clock frequency for register access is 20mhz. 78p2344jat 4-port e3/ds3/sts-1 liu with jitter attenuator - 7 - register description register addressing address bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 port address sub-address read/ write assignment pa[3] pa[2] pa[1] pa[0] sa[2] sa[1] sa[0] r/w* register table a) pa[3:0] = 0 : global registers sub addr reg. name description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 mscr (r/w) master control regen <0> ds3 78p2344jat 4-port e3/ds3/sts-1 liu with jitter attenuator - 8 - register description (continued) legend type description type description r/o read only r/w read or write global registers address 0-0: master control register bit name type dflt value description 7 regen r/w 0 register control enable: 0 : pin selection overrides register settings 1 : device is controlled via register set. note: pin 15 ( endec endec endec endec ) must be tied low when regen is enabled. 6 ds3 r/w x 5 e3 r/w x line speed selection: selects the line speed of all channels as well as the input clock frequency at the ckref pin. [ds3 e3] = 00 : sts-1 (51.840mhz) 01 : e3 (34.368mhz) 10 : ds3 (44.736mhz) 11 : sts-1 (51.840mhz) note: the default values of these register bits depend on the state of the msl0 pin upon power-up or reset. 4 endec r/w 0 encoder/decoder disable: 0 : selects nrz digital data interface 1 : selects ami digital data interface note: relevant only when the regen bit is set. otherwise, endec pin selection prevails. 3 rclkp r/w 0 rclk polarity selection: 0 : receive data clocked out on the falling-edge of rclk 1 : receive data clocked out on the rising-edge of rclk 2 tclkp r/w 0 tclk polarity selection: 0 : transmit data clocked in on the rising-edge of tclk 1 : transmit data clocked in on the falling-edge of tclk 1 rsvd r/o x reserved 0 srst r/w 0 register soft-reset: when this bit is set, all registers are reset to their default values. also resets jitter attenuator to ?centered? states. this register bit is self-clearing. 78p2344jat 4-port e3/ds3/sts-1 liu with jitter attenuator - 9 - register description (continued) address 0-1: interrupt control register this register selects the events that would cause the respective interrupt pin (intrx) for each of the ports to be activated. user may set as many bits as required. bit name type dflt value description 7 inpol r/w 0 interrupt pin polarity selection: 0 : interrupt output is active-low 1 : interrupt output is active-high 6:3 rsvd r/o 0 reserved 2 jaer r/w 0 jitter attenuator error event: when set, jat fifo overflow or underflow (as indicated by the ferr bit) will cause an interrupt to be flagged. 1 rxer r/w 1 receiver error event: when set, loss of receive signal (as indicated by the los bit) will cause an interrupt to be flagged. 0 txer r/w 1 transmitter error event: when set, transmitter fault (as indicated by the txnw bit) will cause an interrupt to be flagged. 78p2344jat 4-port e3/ds3/sts-1 liu with jitter attenuator - 10 - register description (continued) port-specific registers for pa[3:0] = n = 1-4 only. accessing a register with port address greater than 4 constitutes an invalid command, and the read/write operation will be ignored. address n-0: mode control register bit name type dflt value description 7 pdtx r/w 0 transmitter power-down: 0 : normal operation 1 : power-down note: relevant only when the regen bit is set. otherwise, lbox pin selection prevails. 6 pdrx r/w 0 receiver power-down: 0 : normal operation 1 : power-down 5 lbo r/w 1 transmitter line build-out (ds3 and sts-1 only): 0 : 225ft of cable attached to the cross-connect 1 : < 225ft of cable attached to the cross-connect note: relevant only when the regen bit is set. otherwise, lbox pin selection prevails. 4 llbka r/w 0 3 llbkb r/w 0 local (analog) loopback mode selection: [llbka llbkb] = 00 : normal operation 01 : transmitter loopback 10 : adjacent receiver input 11 : adjacent transmitter loopback note: relevant only when the regen bit is set. otherwise, lpbkx pin selection prevails. 2 rlbk r/w 0 remote (digital) loopback enable: 0 : normal operation 1 : loops rclk, rpos, and rneg back onto tclk, tpos, and tneg note: relevant only when the regen bit is set. otherwise, lpbkx pin selection prevails. 1 mon r/w 0 monitor mode enable: used for reception of split-off signals that are flat attenuated by at least 16db but no more than 20db. 0 : disable 1 : enable 0 txen r/w 1 transmitter output enable: 0 : transmit driver is disabled 1 : normal operation note: relevant only when the regen bit is set. otherwise, lbox pin selection prevails. 78p2344jat 4-port e3/ds3/sts-1 liu with jitter attenuator - 11 - register description (continued) address n-1: status monitor register bit name type dflt value description 7 ferr r/o x jitter attenuator fifo error flag: this bit is set whenever a fifo overflow or underflow occurred. it is reset after a read operation to this register. 0 : proper operation 1 : fifo overflow/underflow 6:4 rsvd r/o x reserved 3 los r/o x loss-of-signal indication: 0 : signal detector detecting a valid receive input signal 1 : standards-based loss-of-signal indication note: rposx and rnegx are forced low when los=?1?. rclk will continue to output a line rate clock 2 txnw r/o x transmitter not-working indication: 0 : transmitter ok 1 : transmitter not working 1 rsvd r/o x reserved 0 sglo r/o x signal low indication: 0 : receive signal level ok 1 : receive signal level too low / loss of signal 78p2344jat 4-port e3/ds3/sts-1 liu with jitter attenuator - 12 - register description (continued) address n-3: jitter attenuator control register bit name type dflt value description 7 jaen r/w x jitter attenuator enable: 0 : disables jitter attenuation function 1 : enables jitter attenuation function note: the default values of these register bits depend on the state of the msl1 pin upon power-up or reset. 6 jasl r/w x jitter attenuation selection: 0 : jitter attenuator on the receive path 1 : jitter attenuator on the transmit path note: the default values of these register bits depend on the state of the msl1 pin upon power-up or reset. 5 jlbk r/w 0 jitter attenuator local loopback enable: 0 : normal operation 1 : tclkx, tposx, tnegx connected to jat input and rclkx, rposx, rnegx connected to jat output note: if both rlbk and jlbk bits are set, rlbk mode takes priority. 4 rsvd r/w 0 reserved. must be set to zero. 3:2 esp [1:0] r/w 11 fifo elastic store pointer selection: 00 : pass-through 01 : 8 ui 10 : 16 ui 11 : 32 ui 1 rsvd r/w 0 reserved. must be set to zero. 0 jabw r/w x jitter attenuator bandwidth selection: 0 : low bandwidth 1 : high bandwidth (see jat bandwidth selection table on page 5) note: the default values of these register bits depend on the state of the msl1 pin upon power-up or reset. if the state of the msl0 pin selects e3 or ds3 mode, the default value of jabw is ?0?. if the state of the msl0 pin selects sts1 mode, the default value of jabw is ?1?. 78p2344jat 4-port e3/ds3/sts-1 liu with jitter attenuator - 13 - pin description legend type description type description a analog pin cit cmos 3-state input ci cmos digital input co cmos digital output ciu cmos digital input w/ pull-up coz cmos tristate digital output cid cmos digital input w/ pull-down s supply cis cmos schmitt trigger input g ground transmitter pins name pin type description tposx 23, 31 39, 47 ci transmit positive data/transmit nrz: when endec bit =?1?, a logic one on this pin generates a positive ami pulse on the coax. this pin should not be high at the same time that corresponding tnegx is high. when endec bit =?0?, data on this pin is encoded and converted into positive and negative ami pulses. tnegx 24, 32 40, 48 ci transmit negative data: when endec bit =?1?, a logic one on this pin generates a negative ami pulse on the coax. this pin should not be high at the same time that corresponding tposx is high. when endec bit =?0?, this pin is ignored. tclkx 25, 33 41, 49 cis transmitter clock input: this signal is used to latch the respective tposx and tnegx signals into the 78p2344jat. loutpx loutnx 98, 92 85, 79 99, 93 86, 80 a line out: differential ami outputs. requires a 1:2ct center-tapped transformer and a shunt termination resistor. see application information section for more info. 78p2344jat 4-port e3/ds3/sts-1 liu with jitter attenuator - 14 - pin description (continued) receiver pins name pin type description ckref 57 cis reference clock input: this clock should be from a clean source ( 20 ppm) and represents the line-rate frequency as follows: e3 : 34.368 mhz ds3: 44.736 mhz sts-1: 51.840 mhz rclkx 27, 35 43, 51 co receive clock: recovered receive clock. note: during los conditions, rclkx will continue to output a line rate clock rnegx 28, 36 44, 52 co receive negative data: when endec bit =?1?, this pin indicates reception of a negative ami pulse on the coax. w hen endec bit =?0?, this pin outputs a one when a receive line code violation is detected. rposx 29, 37 45, 53 co receive positive data/nrz data: when endec bit =?1?, this pin indicates reception of a positive ami pulse on the coax cable. when endec bit =?0?, it outputs decoded nrz data. linpx linnx 96, 90 83, 77 95, 89 82, 76 a line in: differential ami inputs. should be 1:1 transformer-coupled and terminated with a shunt resistor. see application information section for more info. control and status pins name pin type description msl0 19 cit data-rate mode selection: low = e3 mode high = ds3 mode float = sts-1 mode note: pin state is latched-in on rising-edge of por signal msl1 20 cit jitter attenuator mode selection: low = jat in receive path high = jat in transmit path float = jat is bypassed note: pin state is latched-in on rising-edge of por signal por 14 a chip reset (active-low): forces hardware reset on device. see description on internal power- on reset for complete use of this pin. endec 15 cid endec enable (active-low): set high to disable internal endec function. note: relevant only when the regen bit is ?0?. pin must be held low when the regen bit is set. 78p2344jat 4-port e3/ds3/sts-1 liu with jitter attenuator - 15 - pin description (continued) control and status pins (continued) lbox 5, 6 7, 8 cit line build-out: low = used with 225ft or more of cable. high = used with less than 225ft of cable. float = disable and power down transmitter. [txen=0; pdtx=1] note: relevant only when the regen bit is ?0?. pin state sampled approximately once every 0.5ms. lpbkx 10, 11 12, 13 cit loopback enable: low = normal operation high = local loopback. transmitter looped back to receiver float = remote loopback. receiver looped back to transmitter note: relevant only when the regen bit is ?0?. pin state sampled approximately once every 0.5ms. intrx 64, 63 62, 61 co interrupt flag: this pin is normally high when the inpol bit is ?0? (default), and normally low when the inpol bit is ?1?. when an interrupt event occurs (as defined in the interrupt control register description), the respective intrx pin will change state. serial-port pins name pin type description cs 65 ci chip select: high during write and read operations. low disables the serial port. while cs is low, sdo remains in high impedance state, and sdi and sck activities are ignored. sck 66 cis serial clock: controls the timing of sdi and sdo. sdi 68 ci serial data input: inputs mode and address information. also inputs register data during a write operation. both address and data are input least significant bit first. sdo 67 coz serial data output: outputs register information during a read operation. data is output least significant bit first. power and ground pins it is recommended that all supply pins be connected to a single power supply plane and all ground pins be connected to a single ground plane. name pin type description vcc 1, 2, 3, 4, 17, 59, 72, 73, 74, 75 s analog power supply gnd 18, 60, 78, 81, 84, 87, 91, 94, 97, 100 s analog ground vccd 16, 22, 30, 38, 46, 54, 55, 58 s digital power supply gndd 9, 21, 26, 34, 42, 50, 56, 69 s digital ground 78p2344jat 4-port e3/ds3/sts-1 liu with jitter attenuator - 16 - electrical specifications absolute maximum ratings operation beyond these limits may permanently damage the device. parameter rating supply voltage (vcc/vccd) -0.5 to 4.0 vdc storage temperature -65 to 150 c junction temperature -40 to 125 c pin voltage (loutpx, loutnx) vcc + 1.5 vdc pin voltage (all other pins) -0.3 to (vcc+0.6) vdc pin current 100 ma recommended operating conditions unless otherwise noted all specifications are valid over these temperatures and supply voltage ranges. parameter rating dc voltage supply (vcc/vccd) 3.0 to 3.6 v ambient operating temperature -40 to 85c dc characteristics: parameter symbol conditions min nom max unit supply current idd all channels on ds3 mode jat enabled: jat disabled: 340 315 370 345 ma ma receive-only supply current iddr all channels pdtx = 1 ds3 mode jat enabled: jat disabled: 132 108 ma ma transmit-only supply current iddt all channels pdrx = 1 ds3 mode jat enabled: jat disabled: 242 218 ma ma supply current per port (including transmitter current through transformer) iddx ds3 mode jat enabled: jat disabled: 82 76 ma ma power-down current iddq ds3 mode pdtx = 1, pdrx = 1 all clocks off 11 15 ma 78p2344jat 4-port e3/ds3/sts-1 liu with jitter attenuator - 17 - electrical specifications (continued) analog pins characteristics: the following table is provided for informative purpose only. not tested in production. parameter symbol conditions min nom max unit linpx and linnx common-mode bias voltage vblin ground reference 1.9 2.25 2.6 v linpx and linnx differential input impedance rilin 10 k ? por input impedance ripor 5 k ? digital i/o characteristics: pins of type ci, ciu, cid: parameter symbol conditions min nom max unit input voltage low vil 0.8 v input voltage high vih 2.0 v input current iil, iih -1 1 a pull-up resistance rpu type ciu only 38 56 78 k ? pull-down resistance rpd type cid only 38 56 78 k ? input capacitance cin 8 pf pins of type cis: parameter symbol conditions min nom max unit low-to-high threshold vt+ 1.3 1.7 v high-to-low threshold vt- 0.8 1.2 v input current iil, iih -1 1 a input capacitance cin 8 pf 78p2344jat 4-port e3/ds3/sts-1 liu with jitter attenuator - 18 - electrical specifications (continued) pins of type cit: parameter symbol conditions min nom max unit input voltage low vtil 0.8 v input voltage high vtih 2.0 v minimum impedance to be considered as ?float? state rtiz 30 k ? pins of type co and coz: parameter symbol conditions min nom max unit output voltage low vol iol = 8ma 0.4 v output voltage high voh ioh = -8ma 2.4 v output transition time tt c l = 20pf; (20-80%) 6 ns pin capacitance cout 8 pf effective source impedance rsrc 30 ? tristate output leakage current iz type coz only -1 1 a 78p2344jat 4-port e3/ds3/sts-1 liu with jitter attenuator - 19 - electrical specifications (continued) serial-port timing characteristics: parameter symbol condition min typ max unit cs or sdi to sck setup time t su 4 ns cs or sdi to sck hold time t h 4 ns sck to sdo propagation delay t prop 5 12 ns 1 sa0 sa1 sa2 pa0 pa1 pa2 pa3 z sen sck sdi sdo t su t h x x or z t su t h d0 d1 d2 d3 d4 d5 d6 d7 z t prop read operation 0 sa0 sa1 sa2 pa0 pa1 pa2 pa3 d0 d1 d2 d3 d4 d5 d6 d7 z sen sck sdi sdo t su t h x x t su t h write operation 78p2344jat 4-port e3/ds3/sts-1 liu with jitter attenuator - 20 - electrical specifications (continued) transmitter timing characteristics: parameter symbol conditions min nom max unit clock duty cycle ttcf/ttc 40 60 % setup time ttdps 2.5 ns hold time ttdph 2.5 ns timing diagram: transmitter waveforms (e3/ds3/sts-1) tclk tclkp=low tclk tclkp=high tpos tneg ttc ttdps ttdph ttdns ttdnh ttcf 78p2344jat 4-port e3/ds3/sts-1 liu with jitter attenuator - 21 - electrical specifications (continued) receiver timing characteristics: parameter symbol conditions min nom max unit ckref duty cycle -- 40 60 % ckref frequency stability -- w.r.t. line-rate frequency -20 +20 ppm rclk duty cycle trcf/trc 40 60 % data propagation delay tprop -2 3 ns timing diagram: receive waveforms (e3/ds3/sts-1) rclk rclkp=low rclk rclkp=high rpos rneg receive line input (ref) (linp,linn) trc trcf tprop tprop 78p2344jat 4-port e3/ds3/sts-1 liu with jitter attenuator - 22 - electrical specifications (continued) ds3 transmitter parameter condition min typ max unit transmitter amplitude measured at loutp/loutn pins w/ 37.5 ? load and lbo pin held high. 700 800 850 mvpk transmitter amplitude mismatch ratio of amplitudes of positive and negative pulses measured at pulse peaks. 0.9 1.1 transmitter power at 22.368 mhz all ones pattern, 3khz bandwidth -1.8 +5.7 dbm harmonic power at 44.736 mhz all ones pattern power below fundamental at 22.368mhz -20 dbm sts-1 transmitter parameter condition min typ max unit transmitter amplitude measured at loutp/loutn pins w/ 37.5 ? effective load and lbo pin held high. 700 825 950 mvpk transmitter amplitude mismatch ratio of amplitudes of positive and negative pulses measured at pulse peaks. 0.9 1.1 transmitter power prbs15 pattern band-limited to 207.36mhz. -2.7 +4.7 dbm e3 ? transmitter parameter condition (see timing diagram) min typ max unit transmitter amplitude measured at loutp/loutn pins w/ 37.5 ? load. 900 1000 1100 mvpk transmitter amplitude mismatch ratio of amplitudes of positive and negative pulses measured at pulse centers 0.95 1.05 transmitter pulsewidth mismatch ratio of widths of positive and negative pulses measured at pulse half amplitude 0.95 1.05 transmitter pulsewidth measured at loutp/loutn pins 14.8 ns 78p2344jat 4-port e3/ds3/sts-1 liu with jitter attenuator - 23 - electrical specifications (continued) e3 transmit pulse template 17 ns 8.65 ns 14.55 ns 12.1 ns 24.5 ns 29.1 ns 0.1 0.1 0.1 0.1 0.1 0.1 0.2 0.2 0 0.5 1.0 0.2 78p2344jat 4-port e3/ds3/sts-1 liu with jitter attenuator - 24 - electrical specifications (continued) ds3 transmit pulse template time axis range (ui) normalized amplitude equation upper curve -0.85 < t < -0.68 0.03 -0.68 < t < 0.36 0.03 + 0.5{1+sin[(pi/2)(1+t/0.34)]} 0.36 < t < 1.4 0.08+0.407 e -1.84(t-0.36) lower curve -0.85 < t < -0.36 -0.03 -0.36 < t < 0.36 -0.03 + 0.5{1+sin[(pi/2)(1 + t/0.18)]} 0.36 < t < 1.4 -0.03 -0.2 0 0.2 0.4 0.6 0.8 1 1.2 -1 -0.5 0 0.5 1 1.5 time, unit intervals normalized amplitude 78p2344jat 4-port e3/ds3/sts-1 liu with jitter attenuator - 25 - electrical specifications (continued) sts-1 transmit pulse template sts-1 (transmit template specs) time axis range (t) normalized amplitude equation (a) upper curve -0.85 < t < -0.68 0.03 -0.68 < t < 0.26 0.03 + 0.5{1+sin[(pi/2)(1+t/0.34)]} 0.26 < t < 1.4 0.1+0.61 e -2.4(t-0.26) lower curve -0.85 < t < -0.38 -0.03 -0.38 < t < 0.36 -0.03 + 0.5{1+sin[(pi/2)(1 + t/0.18)]} 0.36 < t < 1.4 -0.03 -0.2 0 0.2 0.4 0.6 0.8 1 1.2 -1 -0.5 0 0.5 1 1.5 time, unit intervals normalized amplitude 78p2344jat 4-port e3/ds3/sts-1 liu with jitter attenuator - 26 - electrical specifications (continued) transmitter output jitter the transmit jitter specification ensures compliance with itu-t g.823 and g.824, telcordia gr-499 core(i) and gr-253-core, and ansi t1.102-1993 for all supported rates. transmit output jitter is guaranteed only if a clean sonet quality transmit clock source is used. transmitter output jitter detector measured jitter a mplitude f1 f2 20db/decade parameter condition min nom max unit 10 hz to 800 khz 0.15 uipp transmitter output jitter 10 khz to 800 khz 0.08 uipp note: filters defined by standards are used for all testing 78p2344jat 4-port e3/ds3/sts-1 liu with jitter attenuator - 27 - electrical specifications (continued) transmit monitor the transmit monitor function looks at the signals on the loutpx and loutnx pins and checks for the existence of a valid signal. the monitor detects the peak of the transmitted signal at the loutpx and loutnx pins and checks that it is between v under and v over at all times. if the peak level is within the voltage threshold window, the txnw signal is low. if the peak level falls outside of the threshold limits for more than approximately 32 bit times, the txnw signal goes high. v tpos - v tneg v peak v over v under time parameter condition min typ max unit v under ds3 mode with lbox=1 sts-1 mode 320 mvpk v under e3 mode ds3 mode with lbox=0 400 mvpk v over ds3 mode with lbox=1 sts-1 mode 1280 mvpk v over e3 mode ds3 mode with lbox=0 1600 mvpk 78p2344jat 4-port e3/ds3/sts-1 liu with jitter attenuator - 28 - electrical specifications (continued) ds3/sts-1 receiver (transformer-coupled) parameter condition min typ max unit mon=0. signal at dsx is 360-850 mvpk. see notes 2, 3 90 850 mvpk mon=1 25 80 mvpk peak differential input amplitude, linpx and linnx mon=0. ds3-high 90 1200 mvpk flat-loss tolerance mon=0. all valid cable lengths. 0 6 db receive clock jitter ds3 mode with 10 hz ? 400 khz a) normal receive mode b) remote loopback mode 0.1 0.06 uipp uipp interfering tone tolerance (see note 5) maximum ratio of interference power to signal power for ber < 10 -8 a) with 0ft cable from dsx b) with 450ft cable from dsx -9 -10 db db note 1: signal source should meet ds3 template of ansi-t102.1993 figure 4 and sts-1 template of ansi- t102.1993 figure 5. loss characteristics of the we728a or rg59b cable should be better than figure c2 of ansi-t102.1993. note 2: min spec corresponds to minimum dsx amplitude, 5.5db of cable loss (450ft) and 6db of flat attenuation. error-free receiver performance is guaranteed for up to 600ft of cable from dsx cross- connect. typical part can handle up to 900ft. note 3: min spec corresponds to amplitude of 425mvpk at dsx, 5.5db of cable loss (450ft) and 20db of flat attenuation. in monitor mode, interfering tone performance is not guaranteed. note 4: in this mode, no noise, jitter, or interfering tone impairments should be added for guaranteed receiver performance. note 5: interfering signal is a non-synchronous sinusoidal tone of 22.368mhz for ds3 or 25.92mhz for sts-1. data is a prbs15 (2 15 -1) pattern. 78p2344jat 4-port e3/ds3/sts-1 liu with jitter attenuator - 29 - electrical specifications (continued) e3 ? receiver (transformer-coupled) parameter condition min typ max unit mon=0 (see note 1) 120 1200 mvpk peak differential input amplitude, linpx and linnx mon=1 (see note 2) 25 100 mvpk flat-loss tolerance mon=0. all valid cable lengths. 0 6 db receive clock jitter with 100hz-800khz filter: a) normal receive mode b) remote loopback mode 0.1 0.06 uipp uipp interfering tone tolerance (see note 3) maximum ratio of interference power to signal power for ber < 10 -8 a) with 0ft cable b) with 900ft cable -9 -10 db db note 1: min spec corresponds to signal amplitude of 950mvpk at source, 12db of cable loss (1100ft) and 6db of flat attenuation. error-free receiver performance is guaranteed for all cable less than 1100ft. typical part can handle up to 1350ft. note 2: min spec corresponds to signal amplitude of 1000mvpk at source, 12db of cable loss (1100ft) and 20db of flat attenuation. in monitor mode, interfering tone performance is not guaranteed. note 3: interfering signal is a non-synchronous e3 signal of the specified power level below the desired e3 signal. both data and interfering signals are prbs23 (2 23 -1) pattern. 78p2344jat 4-port e3/ds3/sts-1 liu with jitter attenuator - 30 - electrical specifications (continued) receiver jitter tolerance the 78p2344jat receive jitter tolerance exceeds all specifications as shown on the graph below. parameter condition min nom max unit receiver high frequency jitter tolerance > 60 khz 0.75 uipp 10 -2 10 -1 10 0 10 1 10 2 10 3 10 4 10 1 10 2 10 3 10 4 10 5 10 6 10 7 jitter tolerance: 78p234x vs. standards 78p234x core(i) [ds3] core(ii) [ds3] core(ii) [sts1] jitter frequency (hz) jat enabled gr-253- itu - t g.823 [e3] itu - t g.824 [ds3] gr-499- gr-499- jitter tolerance (uip-p) 78p2344jat 4-port e3/ds3/sts-1 liu with jitter attenuator - 31 - electrical specifications (continued) receiver jitter transfer function the receiver clock recovery loop characteristics are such that the receiver has the following transfer function. when the jitter attenuator (jat) is enabled in the receive or transmit path, the receiver or transmitter will exhibit a jitter transfer as shown in the graph and table below. jitter attenuator operation is guaranteed through digital scan testing. the actual jitter transfer is guaranteed by logic design and is not tested during production testing. parameter condition min nom max unit receiver jitter transfer function below fc 0.1 db receiver jitter bandwidth, fc at ?3db point jabw= 0, e3 mode (default) jabw= 1, e3 mode jabw= 0, ds3 mode (default) jabw= 1, ds3 mode jabw= 0, sts1 mode jabw= 1, sts1 mode (default) jaen= 0, jat disabled 13 188 17 245 20 283 55 hz jitter transfer function roll-off after fc 20 db per decade -50 -40 -30 -20 -10 0 10 jitter frequency jitter transfer (db) 10 100 1k 10k 100k 1m etsi tbr 24 (e3) g r - 2 5 3 c a t i ( d s 3 ) e3 jat ds3 jat sts1 jat jat disabled g r - 4 9 9 c a t i ( d s 3 ) g r - 2 5 3 c a t i i ( s t s 1 ) g r - 4 9 9 c a t i i ( d s 3 ) 40hz 1khz 27hz 40khz 59.6khz 78p2344jat 4-port e3/ds3/sts-1 liu with jitter attenuator - 32 - application information external components: component pin(s) value units tolerance receiver termination resistor linpx linnx 84.5 ? 1% transmitter termination resistor loutpx loutnx 402 ? 1% transformer specifications: component value units tolerance turns ratio for the receiver 1:1 turns ratio for the transmitter (center-tapped) 1:2ct suggested manufacturer: pulse, tdk, halo thermal information package conditions ja ( ? c/w) standard 100-pin jedec lqfp (78p2344jat-igt) 46 exposed pad 100-pin jedec lqfp (78P2344JAT-IEL) no forced air, die attach pad soldered to pcb 24.8 schematics for the latest typical application schematics, please check tdk semiconductor's website or contact your local sales representative for the latest application note(s) and/or demo board manuals. 78p2344jat 4-port e3/ds3/sts-1 liu with jitter attenuator - 33 - mechanical specifications (top view) 15.7 (0.618) 16.3 (0.641) pin no. 1 indicator + 15.7 (0.618) 16.3 (0.641) 13.8 (0.543) sq 14.2 (0.559) 1.40 (0.055) 1.60 (0.063) 0.00(0) 0.20 (0.008) 0.60 (0.024) typ. 0.50 typ. (0.0197) 0.18( 0.007) 0.27 (0.011) 78p2344jat-igt mechanical specification 100-pin tqfp (jedec lqfp) 78p2344jat 4-port e3/ds3/sts-1 liu with jitter attenuator - 34 - mechanical specifications (bottom view) max. 1.600 0.500 14.000 +/- 0.100 0.220 +/- 0.050 0.600 +/- 0.150 1.400 +/- 0.050 0.100 +/- 0.050 16.000 +/- 0.200 10.000 max. 10.000 max. max. exposed pad area 16.000 +/- 0.200 100 1 78P2344JAT-IEL mechanical specification 100-pin exposed pad lqfp (jedec lqfp) 78p2344jat 4-port e3/ds3/sts-1 liu with jitter attenuator - 35 - package information pin-out (top view) 78p2344jat 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 63 62 61 60 59 58 57 56 55 54 53 52 51 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 linp3 gnd loutn1 loutp1 gnd linp1 linn1 gnd loutn2 loutp2 gnd linp2 linn2 n/c gnd loutn3 loutp3 gnd linn3 loutn4 loutp4 gnd linp4 linn4 gnd tpos3 tclk4 tneg4 tpos4 vccd rpos3 rneg3 rclk3 gndd tclk3 tneg3 vccd rneg2 rpos2 rclk2 gndd tclk2 tneg2 tpos2 vccd rpos1 rneg1 rclk1 gndd gndd vcc vcc vcc vcc vccd gndd gndd tpos1 tneg1 tclk1 lbo1 lbo2 lbo3 lbo4 vccd lpbk1 lpbk2 lpbk3 lpbk4 gnd vcc msl0 msl1 endec por intr2 intr1 intr3 intr4 sdo n/c n/c vcc vcc vcc vcc gnd vcc vccd sdi sck cs vccd vccd rpos4 rneg4 rclk4 gndd gndd ckref 100-pin tqfp (jedec lqfp) ordering information part description order number package mark 100-pin jedec lqfp 78p2344jat-igt 78p2344jat-igt 100-pin jedec lqfp, no jitter attenuator 78p2344-igt 78p2344-igt 100-pin jedec lqfp w/ exposed solder pad 78P2344JAT-IEL 78P2344JAT-IEL 100-pin jedec lqfp w/ exposed solder pad, no jitter attenuator 78p2344-iel 78p2344-iel tape & reel option append ?r? n/a lead-free option append ?/f? append ?/f 78p2344jat 4-port e3/ds3/sts-1 liu with jitter attenuator - 36 - revision history revision date: revision description: june 24, 2002 endec pin addition (pin 15) and default change to endec bit changed lbox pin functionality by adding txen & pdtx control corrected lpbkx pin description and intrinsic transmit jitter spec. july 10, 2003 changed to preliminary status added exposed pad package option (-iel) and lead-free option (/ f) updated receive jitter tolerance and jitter transfer graphs removed sghi bit definition updated internal power on reset description added pin type cit updated timing diagrams & e-spec table values changed recommended rx / tx termination resistor values to 84.5 / 402 ohm respectively added thermal information section preliminary data sheet: this preliminary data sheet describes a product not completely released to production. the specifications are based on preliminary evaluations and may not be accurate. samples of the described product are available and limited quantities can be purchased. tdk semiconductor corporation should be consulted contacted for contacted to obtain the most current up-to-date inf ormation about the product. if and when manufactured and sold, this product is sold subject to the terms and conditions of sale supplied at the time of ord er acknowledgment, including those pertaining to warranty, patent infringement and limitation of liability. tdk semiconductor co rporation (tsc) reserves the right to make changes in specifications at any time without notice. accordingly, the reader is cautioned to verify that a data sheet is current before placing orders. tsc assumes no liability for applications assistance. tdk semiconductor corp., 6440 oak canyon rd., irvine, ca 92618 tel (714) 508-8800, fax (714) 508-8877, http://www.tdksemiconductor.com ? 2003 ? t d k s e m i c ond u c t or cor p ora t ion 07 / 10 / 03 ? rev 1 . 8 |
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